The invention relates to a neural integrated circuit, comprising:
a memory M for synaptic coefficients Cij
a memory for neuron states
resolving means for determining states of output neurons I on the basis of states of input neurons j,
learning means for determining new synaptic coefficients Cij by performing local learning steps.
The invention also relates to a neural network system comprising a processing device for cooperation with such a neural circuit.
A circuit of this kind is known from the document "A fully digital CMOS integrated feedback network including the learning process", M. Weinfeld, G. Dreyfus, A. Johannet, L. Personnaz, Neural Networks for computing, Snowbird, Utah, Apr. 6-9, 1988.
The cited document concerns an integrated circuit which executes resolving steps and learning steps on the basis of the Widrow-Hoff learning rule. In this circuit parallelism exists as regards the states of output neurons i. The circuit also has a mechanism for the circulation of data which is applied to the index i of the states of input neurons j. It follows therefrom that a particular treatment cannot be isolated to a given neuron. Thus, this circuit can operate with a limited number of learning rules only.
The problem faced by the invention is to realize a neural integrated circuit which is suitable for use in a neural network system comprising a processing device, is capable of operating at high speeds for simultaneously updating all synaptic coefficients of a given output neuron i, and is also capable of executing the bulk of the learning rules so that it can be used for solving the multitude of problems to be dealt with by neural network systems.